September 28, 2006 – Silicon Line GmbH, a German analog and mixed signal IC design company, today announced the development of an 1.25 Gigabit per second (Gb/s) dual-channel clock and data recovery (CDR) IC.
The dual CDR chip provides simultaneous resynchronization capabilities for both directions of a Gigabit communication link in a very compact device. It operates at 1.25 Gb/s on 8B/10B encoded serial data.
The function of this chip is to clean up deterministic and random jitter of e.g. a full-duplex 1000BASE-X link.#
“With the dual CDR development Silicon Line has proven its competencies in the field of low-jitter, low-power PLL devices” said Holger Hoeltke, Managing Director at Silicon Line. “World-wide, the device is one of the smallest dual CDRs designed ever and allows our customer to build multi-channel full-duplex gigabit systems without trading in performance or dealing with power consumption issues.”
The dual CDR chip operates from a single 1.2 V power supply and exhibits a power consumption of less than 20 mW for both channels. It accepts a peak-to-peak input jitters of up to 0.75 UI. The cleaned-up output signal features a peak-to-peak output jitter of less than 0.1 UI. The device allows for system as well as line loopback. Both integrated CDRs can be enabled separately.
The chip was developed in a standard 130 nm CMOS process technology and has a chip size of only 0.7 mm².
To facilitate assembly in small form factor packages and to reduce assembly cost further the dual CDR integrates all necessary functions on chip. No external components are needed to operate the device.